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19-1487; Rev 1; 10/01
MAX3880 Evaluation Kit
General Description
The MAX3880 evaluation kit (EV kit) simplifies evaluation of the MAX3880 2.488Gbps, SDH/SONET 1:16 deserializer with clock recovery. The EV kit requires only a single +3.3V supply and includes all the external components necessary to interface with 3.3V CML inputs and LVDS output logic. The board can be connected to the output of a limiting amplifier circuit (such as the MAX3866) and to the input of an LVDS device (such as an overhead termination circuit). A signal generator or stimulus system can be used with an oscilloscope to evaluate the MAX3880's basic functionality. o Single +3.3V Supply o Test Point for Monitoring Loss-of-Lock (LOL) o Fully Assembled and Tested Surface-Mount Board
Features
Evaluates: MAX3880
Ordering Information
PART MAX3880EVKIT TEMP. RANGE -40C to +85C IC PACKAGE 64 TQFP-EP
Component List
DESIGNATION QTY C1, C2, C3, C6, C8, C15, C16, C17 C4, C5, C7, C12, C13, C14, C19, C20, C21 C9 C10 C11 C22 D1 J1-J4 J5-J40 L1, L2, L3 R1 R2, R3 R4 R5, R6, R11, R13, R14, R16, R17, R19, R20, R22, R23, R25, R26, R28, R29, R31, R32, R34, R35, R37, R38, R40, R41, R43, R44, R46, R47, R49, R50, R51, R52, R54, R55, R57, R58 8 DESCRIPTION 0.1F, 25V min, 10% ceramic capacitors (0603) 100pF, 25V min, 10% ceramic capacitors (0603) 33F 10%, 10V min tantalum caps Sprague 293D336X0010C2 2.2F 10%, 10V min tantalum caps Sprague 293D225X0010A2 Not installed 1F, 25V min, 10% ceramic capacitor (0805) PC mount LED SMA connectors (PC mount) SMB connectors (PC mount) 56nH inductors Coilcraft 0805CS-560XKBC 2k variable resistor 1k, 1% resistors (0603) 392, 1% resistor (0603) None None 1 1 DESIGNATION QTY R7, R12, R15, R18, R21, R24, R27, R30, R33, R36, R39, R42, R45, R48, R53, R56, R59 U1 GND, +3.3V JH1, JH2 JU1-JU5 JU6, JU7 JU6 JU7 DESCRIPTION
17
100, 1% resistors
9 1 1 1 1 1 4 36 3 1 2 1
1 2 2 5 2 1 1
MAX3880ECB (64-pin TQFP-EP) Test points Not installed Not installed Shunts 3-pin header (0.1" centers) 2-pin headers (0.1" centers) MAX3880 evaluation kit circuit board (Rev. B) MAX3880 data sheet
Component Suppliers
35 Not installed SUPPLIER Coilcraft Sprague PHONE 847-639-6400 603-224-1961 FAX 847-639-1469 603-224-1430
Note: Please indicate that you are using the MAX3880 when contacting these component suppliers.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
MAX3880 Evaluation Kit Evaluates: MAX3880
Detailed Description
The MAX3880 EV kit simplifies evaluation of the MAX3880 1:16 deserializer with clock recovery. The EV kit operates from a single +3.3V supply and includes all the external components necessary to interface with 3.3V CML inputs and LVDS outputs.
Loss-of-Lock Monitor
Phase-locked loop (PLL) frequency lock conditions can be monitored at the high-impedance loss-of-lock (LOL) test point. A TTL high (LED off) indicates PLL frequency lock, while a TTL low (LED on) indicates a loss-of-lock condition. Note that the LOL circuitry will not detect a loss-of-power condition (refer to the MAX3880 data sheet).
Connections
Input terminals for the differential 2.488Gbps serialdata input (SDI+, SDI-, SLBI+, SLBI-) are AC-coupled to on-board SMA connectors. Limiting amplifiers with differential output swings between 50mVp-p and 800mVp-p can be connected directly to the SMA connectors. All LVDS outputs (PCLK+, PCLK-, PD_+, PD_-) are differentially terminated with 100 resistors between complementary outputs. Each output can directly drive a high-impedance input oscilloscope (see Connecting to 50 Oscilloscope Inputs in the Applications Information section). When driving an LVDS input that already includes 100 differential termination, remove the termination resistor corresponding to the appropriate LVDS output. The synchronization input (SYNC+, SYNC-) is an LVDS input internally terminated with 100 differential input resistance. Ensure that LVDS devices driving this input are not redundantly terminated. All signal inputs and outputs use coupled 50 transmission lines. All output signal lines are of equal length to minimize propagation-delay skew.
Layout Considerations
The MAX3880's performance can be greatly affected by circuit-board layout and design. Use good high-frequency design techniques, including minimizing ground inductances and using fixed-impedance transmission lines on the data and clock signals.
Table 1. Jumpers and Test Points
NAME TYPE DESCRIPTION Selects between the serial-data input and the system loopback function of the MAX3880. Disables PHADJ (R1) Monitors LOL voltage level NORMAL POSITION Shorted between 2, 3 Shorted (disabled) -
JU6
3-pin
JU7 LOL
2-pin Test Point
Applications Information
Connecting LVDS Outputs to 50 Oscilloscope Inputs
To monitor an LVDS signal on a 50 input oscilloscope, remove the differential load resistor between the complementary outputs and AC couple each output to an oscilloscope input. For example, to observe the PD0 signal on a 50 input instrument, remove resistor R15 from the EV board and place a capacitor or DC block in series with each output (PD0+ or PD0-) and the instrument input. Do not connect MAX3880 outputs directly to 50 inputs or terminations to ground. Choose a coupling capacitor large enough in value to prevent pattern-dependent distortion of the output signal.
Setup
1) Select either the serial-data inputs, pins 2 and 3 of JU6 (SDI EN), or the system loopback inputs, pins 1 and 2 of JU6 (SLBI EN) with a 2-pin jumper. 2) Verify that the shunt across jumper JU7 is in place. 3) Connect the +3.3V power supply to the appropriate terminals marked on the EV kit and apply power. 4) Connect a 2.5Gbps NRZ data signal (<800mVp-p differential) to the selected inputs with 50 cables. 5) Connect the LVDS outputs to a high-impedance oscilloscope or refer to the Applications Information section.
Phase Adjustment
Internal phase adjustment is available on the MAX3880 EV kit. Phase adjust (PHADJ) R1, although not required, can be used to shift the sampling edge of the recovered clock relative to the center of the data eye. Ensure JU7 is removed when adjusting PHADJ.
Exposed Pad (EP) Package
The exposed pad 64-pin TQFP incorporates features that provide a very low thermal resistance path for heat removal from the integrated circuit--either to a printed circuit board or to an external heatsink. The MAX3880's exposed pad must be soldered directly to a ground plane with good thermal conductance.
2
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MAX3880 Evaluation Kit Evaluates: MAX3880
JH1 1 3 PD15PD14PD13PD12PD11PD10PD9PD85 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 PD15+ PD14+ PD13+ PD12+ PD11+ PD10+ PD9+ PD8+
JH2 1 PCLKPD7PD6PD5PD4PD3PD2PD1PD03 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 PCLK+ PD7+ PD6+ PD5+ PD4+ PD3+ PD2+ PD1+ PD0+
L3 56nH IN1 +3.3V L1 56nH C9 33F 10V GND C10 2.2F 10V
C15 0.1F
C7 100pF
VCC_VCO
C16 0.1F
C12 100pF
C13 100pF
C14 100pF
VCC_PLL
L2 56nH
C17 0.1pF
C19 100pF
C20 100pF
C21 100pF
C4 100pF
C5 100pF
VCC
Figure 1. MAX3880 EV Kit Schematic _______________________________________________________________________________________ 3
MAX3880 Evaluation Kit Evaluates: MAX3880
PD15PD15+ R5 OPEN J39 R6 OPEN J40 PD14+
PD14PD13+ R57 OPEN J37 R58 OPEN J38
PD13PD12+ R54 OPEN J35 R55 OPEN J36
PD12R51 OPEN J33 R52 OPEN J34
R7 100 1%
R59 100 1%
R56 100 1%
R53 100 1%
VCC_PLL D1 +3.3V +3.3V R3 1k 2 1 R2 1k JU7 R11 OPEN JU4 C22 0.1F 3 PHASE ADJUST R1 JU3 JU2 VCC C11 R4 0.1F 390 TP1 VCC JU1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PD15+ GND PD15PD14+ PD14GND LOL PD13+ PD13PD12+ PD12PD11+ PD11GND GND VCC 1 2 3 4 5 6 C3 0.1F VCC_PLL 7 8 9 VCC_PLL 10 11 12 +3.3V J3 SLB+ J5 J4 SLBC8 0.1F SYNC+ SYNCJ6 C6 0.1F 1 JU6 3 2 VCC_PLL 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
GND FIL+ FILVCC PHADJ+ PHADJVCC SDI+ SDIVCC SLBI+ SLBIVCC SIS SYNCPCLK+ PCLKSYNC+
VCC PD10+ PD10PD9+ PD9PD8+ PD8GND VCC PD7+ PD7PD6+ PD6PD5+ PD5GND VCC VCC R21 100 1% J14 R23 OPEN
JU5 J1 SD+ C1 0.1F C2 0.1F
VCC_VCO
U1 MAX3880
J2 SD-
PD0+
PD1+
PD2+
PD3+ PD2-
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VCC R12 100 1% J8 R13 OPEN PCLKPCLK+ R14 OPEN PD0PD0+ R16 OPEN R17 OPEN PD1PD1+ R15 100 1% J10 R19 OPEN R20 OPEN R18 100 1% J12 R22 OPEN
J7
J9
J11
J13
Figure 1. MAX3880 EV Kit Schematic (continued) 4 _______________________________________________________________________________________
PD4+
PD0-
PD1-
PD2-
PD3-
PD4-
GND
GND
VCC
PD2+
MAX3880 Evaluation Kit Evaluates: MAX3880
PD11PD11+ R46 OPEN J29 R47 OPEN J30 PD10+
PD10R49 OPEN J31 R50 OPEN J32
R48 100 1%
R45 100 1%
VCC PD10+ PD10PD9+ PD9PD8+ PD8GND VCC PD7+ PD7PD6+ PD6PD5+ PD5GND PD6PD8-
J25
R39 100 1% J26
J27
R42 100 1% J28
R40 OPEN R41 OPEN PD8+ PD9-
R43 OPEN R44 OPEN PD9+
J21
R33 100 1% J22
J23
R36 100 1% J24
R34 OPEN R35 OPEN PD6+ PD7-
R37 OPEN R38 OPEN PD7+
J19
R30 100 1% J20
J15
R24 100 1% J16
J17
R27 100 1% PD5J18
R31 OPEN R32 OPEN PD5+
R25 OPEN PD3PD3+ R26 OPEN PD4-
R28 OPEN R29 OPEN PD4+
Figure 1. MAX3880 EV Kit Schematic (continued) _______________________________________________________________________________________ 5
MAX3880 Evaluation Kit Evaluates: MAX3880
Figure 2. MAX3880 EV Kit Component Placement Guide--Component Side 6 _______________________________________________________________________________________
MAX3880 Evaluation Kit Evaluates: MAX3880
Figure 3. MAX3880 EV Kit Component Placement Guide--Solder Side
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7
MAX3880 Evaluation Kit Evaluates: MAX3880
1.0"
Figure 4. MAX3880 EV Kit PC Board Layout--Component Side
8
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MAX3880 Evaluation Kit Evaluates: MAX3880
1.0"
Figure 5. MAX3880 EV Kit PC Board Layout--Solder Side
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MAX3880 Evaluation Kit Evaluates: MAX3880
Figure 6. MAX3880 EV Kit PC Board Layout--Power Plane 10 ______________________________________________________________________________________
MAX3880 Evaluation Kit Evaluates: MAX3880
Figure 7. MAX3880 EV Kit PC Board Layout--Ground Plane
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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